The principle way of reducing contact resistance between polysilicon gates and source/drain regions and interconnect lines is by forming a metal silicide atop the source/drain regions and the gate electrodes prior to application of the conductive film for formation of the various conductive interconnect lines. Presently, the most common metal silicide materials are CoSi2 and TiSi2, typically formed by the so called salicide (self-aligned silicide) process. In the salicide process, a thin layer of a metal, such as titanium, is blanket deposited over the semiconductor substrate, specifically over exposed source/drain and gate electrode regions. The wafer is then subjected to one or more annealing steps, for example at a temperature of 800° C. or higher for titanium. This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrodes, thereby forming a metal silicide (e.g., TiSi2). The process is referred to as the self-aligned silicide process because the silicide layer is formed only where the metal material directly contacts the silicon source/drain regions and the polycrystalline silicon (polysilicon) gate electrode. Following the formation of the silicide layer, the unreacted metal is removed and an interconnect process is performed to provide conductive paths, such as by forming via holes through a deposited interlayer dielectric and filling the via holes with a conductive material, e.g., tungsten.
The thickness of the silicide layer is an important parameter because a thin silicide layer is more resistive than a thicker silicide layer of the same material. Therefore, a thicker silicide layer increases semiconductor speed. The formation of a thick silicide layer, however, may cause a high junction leakage current in the active regions and low reliability, particularly when forming ultra-shallow junctions. The formation of a thick silicide layer consumes silicon from the underlying semiconductor substrate such that the thick silicide layer approaches and even shorts the ultra-shallow junction, thereby generating a high junction leakage current.
It is desirable to also lower the resistance of the gate electrode to increase the speed of the device. The greater the amount of silicon converted into silicide in the gate electrode, the lower the resistance will be in the gate electrode. Silicided gate electrodes also eliminate problems associated with boron penetration from the polysilicon gate electrode into the gate oxide of PMOS devices and avoid device performance degradation due to the depletion effect. Formation of silicide in the gate electrode simultaneously with the source/drain regions leads to the risk of spiking in the source/drain regions if the complete silicidation of the gate electrode is attempted. The conventional salicide process, therefore, suffers from a very narrow process window due to the strong likelihood that exposure of the metal and silicon to rapid thermal annealing conditions sufficient to completely silicidize a gate electrode will also cause the silicide in the source/drain region to spike and reach the bottom of the junction, undesirably causing leakage.
Various methods have been suggested for forming fully silicided gate electrodes. U.S. Pat. No. 6,562,718 to Xiang et al. describes a method of forming a fully silicided gate electrode. Xiang et al. propose simultaneously forming a silicide region in the source/drain regions and partially within the gate electrode. A silicon oxide shielding layer is then deposited over the substrate and opened by chemical mechanical polishing (CMP) to expose the gate electrode, leaving the source/drain regions covered by the remaining portion of the shielding layer. Silicidation of the gate electrode is then completed. The Xiang et al. process suffers from several problems. The CMP step adds significant process costs to the fabrication method. Further, the CMP step adversely effects process control. Specifically, the CMP step is not highly selective between the oxide shielding layer and the polysilicon gate. Therefore, the height of the polysilicon gate cannot be controlled effectively using the process of Xiang et al.
There remains a need for a method of forming fully silicided gate electrodes that affords greater process control.